Power-on reset circuits are used to ensure that a circuit is connected to power only when the power is currently good and has been good for some time. Generally power-on-reset circuits must completely and quickly activate to reset the system upon any indication of poor power quality.
Generally, power-on-reset (POR) pulse generation circuits rely on one of three principles. The first principle is tracking of a process threshold voltage, such as a MOSFET Vt. When the voltage is above the threshold, the POR pulse is sent.
A second principle is sensing an absolute voltage level in comparison to a reference voltage. When the absolute voltage is above the reference voltage, the POR pulse is sent.
The third principle is delay. Once an acceptable voltage level is reached through one of the other methods, a staged R-C or clock/counter delay is generated to ensure that voltages have stabilized.
FIG. 1 illustrates one prior art power-on-reset circuit using these principles. This circuit 110 works, assuming that the V.sub.cc 140 voltage rises quickly and monotonically to its maximum value and stays there. Under those conditions, you can choose an RC time constant large enough to guarantee that the Schmitt-trigger gate 120 holds .about.RESET 130 low (active) for any specified time after V.sub.cc 140 stabilizes. After the RC time-out, .about.RESET goes high (inactive), commencing normal operations.
Conventional power-on reset circuits generally are left running when the circuits are powered down, to detect an external reset of power-up. This results in a less-than-perfect shutdown.
Therefore, an improved power-on reset system may be useful.